This patent relates to a semiconductor device, and more particularly, to a method for manufacturing a dual gate in a semiconductor device.
A semiconductor device, especially a dynamic random access memory (DRAM), has a cell region and a peripheral circuit region. In particular, the peripheral circuit region includes a complementary metal oxide semiconductor (CMOS) transistor. In a general CMOS transistor, a p-type MOS transistor has a buried channel structure. In the buried channel structure, the length of a channel becomes shorter as the integration degree of a device increases. Accordingly, an application of higher electric field may cause degradation of the leakage current characteristics of the semiconductor device. Therefore, a dual gate structure has been employed to realize a p-type MOS transistor having a surface channel structure in recent years.
In a process for manufacturing the dual gate, a gate conductive layer is formed on a gate insulating layer. N-type dopant is implanted into a region in which an n-type MOS transistor is formed, and a p-type dopant is implanted into a region in which a p-type MOS transistor is formed. A thermal diffusion process is performed on an entire semiconductor substrate so that the implanted dopant may be sufficiently diffused on the gate. In the dual gate formed on the semiconductor substrate as described above, the p-type gate implanted with the p-type dopant is formed on the region in which the p-type MOS transistor is disposed, and the n-type gate implanted with the n-type dopant is formed on the region in which the n-type MOS transistor is disposed. The dual gate has a structure with a plurality of metal films stacked on the gate conductive layer and a barrier metal layer interposed between the metal films. In this structure, a process for forming the metal film may be complicated and unstable. Moreover, an etching process for patterning a gate stack may not be easily performed because there are many etch target layers. Accordingly, a gate stack structure is required for stably performing the process of manufacturing the semiconductor device.